Improvements in microprocessor designs have led to microprocessors with a high operating frequency. Current microprocessor designs exceed operating frequencies of 200 megahertz ("MHz"). However, the increase in operating frequency has not led to fully acceptable performance gains. One of the main components affecting performance gains is created by the microprocessor execution units idling during delays in external memory access. The delays in external memory access are caused by the conventional design characteristics of static random access memory ("SRAM") cells, read only memory ("ROM") cells, and dynamic random access memory ("DRAM") cells.
To counteract the performance losses associated with external memory access, Rambus Inc., of Mountain View, Calif. developed a high speed multiplexed bus. FIG. 1 illustrates the Rambus high speed bus. In particular, system 100 shows a master device, central processing unit ("CPU") 10, coupled to slave devices DRAM 20, SRAM 30, and ROM 40. Each device is coupled in parallel to signal lines DATA BUS, ADDR BUS, CLOCK, V.sub.REF, GND, and VDD. DATA BUS and ADDR BUS show the data and address lines used by CPU 10 to access data from the slave devices. CLOCK, V.sub.REF, GND, and VDD are the clock, voltage reference, ground, and power signals shared between the multiple devices. Data is transferred by a single device's bus drivers (not shown) driving signals on the bus. The signals are transmitted across the bus to a destination device.
To increase the speed of external memory accesses system 100 supports large data block transfers between the input/output ("I/O") pins of CPU 10 and a slave device. System 100 also includes design requirements that constrain the length of the transmission bus, the pitch between the bus lines, and the capacitive loading on the bus lines. Using these design requirements system 100 operates at a higher data transfer rate than conventional systems. Accordingly, by increasing the data transfer rate, system 100 reduces the idle time in CPU 10.
System 100, however, does not provide enough bus bandwidth for developing technologies. New technologies require data transfer rates greater than 500 megabits per second ("Mb/s") per pin. Alternatively, new technologies require operation speeds of at least several hundred MHz. Operating at high frequencies accentuates the impact of process-voltage-temperature ("PVT") on signal timings and signal levels. The PVT variances result in numerous disadvantages that create high transmission errors (i.e. data loss) when operating system 100 at a 400 MHz frequency, for example.
One disadvantage of operating system 100 at a speed such as 400 MHz is that system 100 may not provide a desired slew rate at high operating speeds. In particular, the constraints on loading, bus length, and bus pitch in conjunction with block data transfer do not provide for a stable slew rate at 400 MHz. Slew rate describes the rate at which a bus driver switches the voltage on a bus line. Slew rate of the bus driver is an extremely important characteristic for ensuring proper operation at high frequencies.
Another disadvantage of operating system 100 at 400 MHz is that system 100 incurs ringing in the power lines VDD and GND, resulting in signal distortion. Thus, the inductive/capacitive characteristics of the bus and signal lines are exaggerated at a higher frequency resulting in signal distortion. Yet another disadvantage of operating system 100 at 400 MHz is that system 100 cannot provide low error rates. In particular, at high operating frequencies, the simple clocking scheme of system 100 does not guarantee synchronization between transmitted data and the clocking scheme in the destination device. Thus, incorrect data can be captured in a destination device.